Honored Contributor
Honored ContributorI have been able to get this to work with just the plain Megacore version of a FIR filter (I had posted in a different thread....see below). The trick there is that you need to modify your coeff's using an executable provided by Altera (coef_seq.exe), in order to get it to work. If you have plenty of space, it's no big deal to store them (my 11 18-bit coefficients turned into something like 64 24-bit values) and then push them in via the coef_ld ports on the FIR filter. I peeled apart what was actually being done to the values, and it was dividing them up into a massive sum-of-products tree. I was able to mimic this in logic, because I really only had space in my device for 11 of the 18-bit values.
I was able to get the reloadable filter design working on the bench, and was able to manually input coefficients (using Nios) into my custom logic, and it passed the values into the FIR w/ the coef_seq formatting. I was able to create LPF and HPFs w/out reloading the FPGA. Worked out pretty well, although not horribly intuitive. The link to my other post is here: http://www.alteraforum.com/forum/showthread.php?t=838&highlight=fir+reload Anyways, I was wondering if anyone's tried the register-access FIR reload function in the DSP builder advanced blockset. I'm a bit intrigued by it, since it seems like it would work pretty well. From what I can tell, you establish a base address for each module in the design, and then the individual coefficients would be BASE_A+0, BASE_A+1 ... BASE_A+(NUM_COEFF-1), as long as you make the data width wider than the widest coefficient. Can anyone confirm if that assumption is true, before I dive into it? Jeff
