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SnehalB's avatar
SnehalB
Icon for New Contributor rankNew Contributor
2 years ago

FIR filter ip block coefficient update not working or issue

Hi,

we want to use FIR filter IP block from intel on quartus lite prime with cyclone V E fpga in our design. So tried to test and simulate IP working on the model sim as well as on signal tap.

below is some ip setting we did for block related to tap coeffecients. so you can see we set it as 8bit fraction & 16bit coefficient value.

As per that IP generated 16bit coefficient update bus

so we run simulation for testing ip and written 16bit values to different coefficient tap address as given by ip user guide. but when we read out those written value back we get only LSB byte data correct msb byte returned 0. so for 16bit written we get only LSB 16bit only. same we observed on signal tap. we also tried reading all addresses but same issue.

can you check and brief about the ip core behavior. below attached model sim reference .

3 Replies

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    Can you please share which Quartus version you are using and complete device OPN.


    Also, are you giving coefficient into the signed fractional binary format?


    Can you please try with signed binary once.


    Thank you

    Kshitij Goel




    • SnehalB's avatar
      SnehalB
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi,

      we using quartus prime lite 21.1, we have valid FIR 2 filter IP license . cyclone V E part we using is 5CEBA9U19C7.

      yes its signed fractional binary format. we tried that only. same we tried on signal tap also same issue

      thanks,

      Snehal B