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TMK's avatar
TMK
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7 years ago

FIFOed UART Qsys Generation Error with Qsys Standard v18.1

Hello, when generating a FIFOed UART with Qsys Standard v18.1 as provided here https://forums.intel.com/s/createarticlepage?language=en_US&articleid=a3g0P0000005RTHQA2&artTopicId=0TO0P000000MWKBWA4...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
7 years ago

I try it on VHDL and verilog, it get error. Where did you generate this IP? In the IP catalog or in the platform designer?

This IP was created in Q13.1, at that time, it is still using megafunction (not IP catalog) and this IP does not exist in the megafucntion.

You have use this IP in the platform designer. I try it on verilog and vhdl, I am using redhat. No error found when generating the IP.

Thanks

TMK's avatar
TMK
Icon for New Contributor rankNew Contributor
7 years ago

Well, as mentioned earlier I generate this IP in Platform Designer, formerly Qsys. Did you copy the settings from the screenshot to reproduce the problem? Please perform the following steps to reproduce the problem:

  1. Create a Cyclone IV project
  2. Open Platform Designer
  3. Add a FIFOed UART instance
  4. Enable the Tx FIFO
  5. Set synthesis output to VHDL and generate the system