FIFO problem with reading

No I haven't found anything, that happend in simulation but I'm not sure if it happens in real hardware, in simulation I'm using a stub FIFOS to check my logic.

All my logic seem to be working OK. I'm dealing with a problem in a DDR IP controller (EMIF), I have this config: INPUT_FIFO->DDR->OUTPUT_FIFO, I did a lot of ways of writing, this are the scenarios:

1. I write once to the bank 0 and then read to the bank 0 all the time.
2. I write once to the bank 0 wait (100 ms until 1 s) and then read to the bank 0 all the time.
3. I write and read changing in a different way as a circular buffer between Bank 0, Bank 1 and Bank2.
4. Among others ways of the logic.

The noise stuff seems to be the data from another bank, like if the image overlap in that places. I have change a lot of the code and made a lot of test, I have eliminated a lot of possibles causes and in simulation seems that the my logic works ok, the only thing that I can think of is the DDR controller (EMIF), do you know if there is something or an idea?, I'm using the "Cyclone 10 GX FPGA Development Kit".