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Altera_Forum
Honored Contributor
14 years agoFFT Megacore V11.1 problem
Hi all, I am using Terasic's DE2-70 dev board and I am building a windowed FFT processor (8192 points each, 16 non-overlapping windows) using Quartus II and Modelsim-Altera. The megacore uses b...
Altera_Forum
Honored Contributor
14 years agoYes, kaz. That is exactly what I am saying. Matlab fft and testbench (both my own and the altera generated matlab testbench) work perfectly ok. The hardware does not, though. but I am now finding out that when I clock the FFT core at frequencies less than or equal to 10MHz, the output is correct ! I am still doing some tests to see if this works over the entire dynamic range. I will keep the thread posted but I suspect that the FFT core (in my cyclone II device) cannot be clocked too fast.
This actually will cause a problem for me because I will need to change the clocking of my ssram (one frequency during acquisition, and another frequency during FFT), which means I might have to use a gated clock :(