Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThanks for the tips. I have tried the trick, it makes the process proceed to "Generating Verilog HDL IP functional simulation model", but still stuck at this stage forever. Then, I tried the same trick, but it failed the how process. I do need to generate the Simulation model, which cannot be bypassed by killing the quartus_map. Is there any other tricks to play with?
--- Quote Start --- Hi Roger, I've noticed this too - what seems to be happening is that Quartus_map hangs when creating the model for 3rd party synthesis - so what you can do to work around this is open up task manager go to processes and kill quartus_map. That will let it complete for you. Not great, better than nothing! --- Quote End ---