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NAnhT's avatar
NAnhT
Icon for New Contributor rankNew Contributor
2 years ago

FFT IP core. Source SOP does not goes low

Dear support team,
I am using FFT IP core on Quartus 18.1 with following setting


I generated sink SOP and EOP by the counter and I put 1024 samples in the FFT core. I still can get the real and img results at the output. However, the source SOP does not go low and I cannot know when the packet starts after FFT.
Below is the simulation results

I am using a clock of 200Khz. How can I get the right SOP and EOP?
Best regards



3 Replies

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    Can you please share your project, also can you please try with other FFT Method.



    Thank you

    Kshitij Goel


  • NAnhT's avatar
    NAnhT
    Icon for New Contributor rankNew Contributor
    2 years ago

    I have found the solution,
    Weirdly, the clock output from the lower module which provides the clock for the FFT must be output reg. If I use the register in the module and then assign the output with the register, it will not work.
    In my case the lower module is an ADC controller, it sample the analog signal and send it to the FFT block, the ADC and FFT using the same clock and I have to set this clock to output reg.

    I hope that anyone encounter the same problem find this helpful

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘ https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Thank you

    Kshitij Goel