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NAnhT's avatar
NAnhT
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2 years ago

FFT IP core. Source SOP does not goes low

Dear support team, I am using FFT IP core on Quartus 18.1 with following setting I generated sink SOP and EOP by the counter and I put 1024 samples in the FFT core. I still can get the real...
NAnhT's avatar
NAnhT
Icon for New Contributor rankNew Contributor
2 years ago

I have found the solution,
Weirdly, the clock output from the lower module which provides the clock for the FFT must be output reg. If I use the register in the module and then assign the output with the register, it will not work.
In my case the lower module is an ADC controller, it sample the analog signal and send it to the FFT block, the ADC and FFT using the same clock and I have to set this clock to output reg.

I hope that anyone encounter the same problem find this helpful