Feasible Top Level Design of RSU, ASMI with Cyclone V via Ethernet?

Thank you Nooraini for the input on utilizing RPD. The RPD contains 12MB with the header stripped off. Would I be sending the entire file byte addressed including padded FF's? If I recall, the ASMI block can only write 256 bytes via PAGE_SIZE followed by busy signal. I will look into a RSU+ASMI design example since I believe I was working with a RSU Cyclone V template (which may be the same design).

Another question.

Would there be an issue to have only a factory image and writing only to a factory image at address 0x000000 without an application image? In other words, is there a consequence of bricking an FPGA if the RPD file happens to be corrupted? Also, does the sectors have to be erased (set to '1's) before writing into Page 0?

Appreciate the timely response. Thanks

-Steve