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Hi, thanks Pletz for helping me. I had tried to generate to fft block again but still the same result. Somehow I just can't seem to be able to use the block. Maybe the way I generate it is wrong, cause when I tried it in another computer the same error message appear. Let me explain my steps again, see if I missed anything that could lead me to the error.
1. First, I create a new project directory at
c:\altera\projects\fft_project 2. Then, I generate fft megafunction under a project with the name fft.qpf,
so the vhd code generated is located at
c:\altera\projects\fft_project\fft.vhd along with other files such as fft.bsf,
fft.qip, fft_tb.v, fft_tb.vhd and many others.
3. After that, I create another project with the name fftwork.qpf. The
location of the project is
c:\altera\projects\fft_project\fftwork.qpf Under that project, I create a block diagram file (bdf) named fftwork.bdf.
Inside that bdf file, there is the fft block. fft.qip is added to the project
using settings (assignments). I get the same error message result
regardless if I connect the fft block pins or not. The compilation stops at
23% everytime.
Is this a wrong way to use IP megafunction? And also, I tried generating Reed-Solomon decoder with the same method and I still face the same error message. I am running out of idea anymore to solve this problem. Do you have any other suggestions?
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Hi ,
you should install at least the service pack for the 8.0 version. If this does not help you should try the 8.1 version of the Quartus Web edition. BTW you don't need a licence anymore for the 8.1 version. In the meantime I will try to reproduce your problem on my PC. What is your FPGA target family?
GPK
Honored Contributor
