Altera_Forum
Honored Contributor
17 years agoFailed to transfer to modelsim
In the .mdl file,when I used the Testbench model to run modelsim, errers were found in modelsim:
# Reading D:/altera/71/modelsim_ae/tcl/vsim/pref.tcl # source tb_mymodel.tcl # Loading project DspBuilder # vsim -quiet -t {1 ps} work.tb_mymodel_GN2124 # ** Error: Failure to obtain a VHDL simulation ******. # Error loading design # Unrecognized dataset prefix: sim what's the matter? Thanks!