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Altera_Forum
Honored Contributor
Honored Contributorfailed to create fir.vhd
when i managed to use signal compiler to convert fir.mdl to vhdl and failed to create fir.vhdl.i got the error:Entity fir -> block x16: Input pin(1) is not connected to an Altera Block. I was hoping ...
Altera_ForumHonored Contributor
Honored ContributorWhat do you have inside your .mdl? Is it simply one instance of FIR compiler? Perhaps you can post your .mdl here so we can help look at it...
