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Serge93
Occasional Contributor
Occasional ContributorF-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer
Hello Support, I am using the Agilex 7F Dev Kit with F-Tile configured in Root Port Gen3x4. When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh, the end point se...
RongY_altera
Contributor
ContributorI think something is mixed here. Most actions should be done to the type1 config register. But the mem space enable should be written to type0 command.
- Read @82h to get Link Rate and Link width
- Write 00h at @18h
- Read @18h to check previous Write
- Write 01h at @19h
- Read @19h to check previous Write
- Write 01h at @1Ah
- Read @1Ah to check previous Write
- Write 00h at @1Bh
- Read @1Bh to check previous Write
- Write 06h at @04h <------------------------to type0 command
- Read @04h to check previous Write
Regards,
Rong
Serge93Occasional Contributor
Occasional ContributorHello Rong,
All these accesses are done on the configuration space of the RP Pcie directly through the configuration bus.
There is no type 0 or type 1 concern to have.
Thanks.
Serge
