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RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

External Memory Interface IP on Stratix 10

I have a design incorporating the EMIF IP for a Stratix 10 chip (Terasic Apollo S10 dev kit). I generated the design example and simulated it using the Avalon Verification IP Suite and BFM. I’ve read...
Memory
  • RHobb's avatar
    RHobb
    2 years ago

    I solved the problem:

    the waitrequest signal is active low. I was triggering my logic on active high.
    this isn’t immediately relevant from reading the Avalon spec but mere oversight by not seeing the signal in the IP block diagram.

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.