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HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
6 years ago

Explanation on RX Bit slip in Stratix 10 Transceivers

Hi,

I am going through the bit slip logic present in the Receiver path of Stratix 10 L-tile transceiver.

1) This is the basic question prior to getting into bit slip logic. For example, If I send A5A5... pattern as the first data, without RX bit slip, the receiver parallel data will be complete but just shifted version of A5A5 (Like D2 or 4B) or A5A5 could be shared between 2 cycles of parallel data and then we need to stitch from 2 data (from consecutive cycles, like first data will be 00A5 and next data will be A5A5 and so on )?

2) What is the latency between asserting rx_bitslip and there is a shift in the RX parallel data?

3) As per my understanding rx_bitslip causes the parallel data to be shifted left without discarind or appending new data to LSB. But section "5.2.2.1. RX Gearbox, RX Bitslip, and Polarity Inversion" describers that "Each bit slip removes the earliest received bit from the received data." That means it discard the MSB and appends LSB with a '0'. Here, some clarification is required.

With Regards,

HPB

3 Replies

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    HI,

    Pls see my reply below.

    1) bit_slip operation

    • It's doesn't pad extra bit to the data bus
    • What happen is it shifted the capture clock to next clock cycle to capture the next bit data end up like the earliest bit is being removed because it's not sampled
    • End result is still whole data bus looks like shifted to the left

    2) What is the latency between asserting rx_bitslip and there is a shift in the RX parallel data?

    • Intel doesn't has the latency spec.
    • My advise to you is to run sim to check the latency number

    Thanks.

    Regards,

    dlim

    • HBhat2's avatar
      HBhat2
      Icon for Contributor rankContributor
      6 years ago

      Hi @DeshiL_Intel​ ,

      Thanks for your update,

      I have done the simulation and understood the behavior.

      Also, while performing bitslip, following is very crucial thing to take care and this is mentioned in L-tile transciver user guide.

      "The rx_parallel_data slips 1 bit for every positive edge of the rx_bitslip input. Keep the rx_bitslip pulse high for at least 200 ns and each pulse 400 ns apart to ensure the data is slipped."

      With Regards,

      HPB