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Altera_Forum
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14 years ago

Ethernet IP core

Hi, Dose anybody knows if it possible to implement Ethernet communication (10/100 MHz) on FPGA (lets say Cyclone 3…)? Is there any Altera proven VHDL IP core for that? (I don’t what to write...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

In VHDL language, To define an IP_address is really very difficult. But instead of you must have written by C language as I've already said for you.

best wishes!