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Altera_Forum
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14 years ago

Ethernet IP core

Hi, Dose anybody knows if it possible to implement Ethernet communication (10/100 MHz) on FPGA (lets say Cyclone 3…)? Is there any Altera proven VHDL IP core for that? (I don’t what to write...
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Altera_Forum
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14 years ago

The Avalon-ST interconnect to the TSE MAC is 32bit wide. Also the data is transfered when SOP is low, since SOP flag is only asserted on the first 32bit of data.