Mikhail_a
Occasional Contributor
2 years agoEthernet 100g cant be placed at the location on Agilex 7 FPGA
Hello
When synthesis design for AGIB027R31B1E1VAA that contains F-Tile Ethernet Intel FPGA on Intel Agilex ® 7 FPGA I-Series Transceiver-SoC Development Kit I got the next error:
The specified block fm87_top_bd|mac_subsystem_0|mac_100g|eth_f_0|hip_inst|per_xcvr[0].x_bb_f_ux|x_bb_f_ux_rx cannot be placed at the location fgt_q2_ch0_rx as the block requires stream(s) [0] in an Ethernet 100g block but the location only supports stream(s) [1, 2, 3].
Transceivers pins are connected to QSFPDD0 connector. I have the same error for QSFPDD1 connector. IP settings are shown below. Pins assignments were taken from design example in agilex_agib027r31b1e1vaa_si_en_revb_v23.1b115_v1.0.zip archive.
F-Tile Reference and System PLL Clock Intel® FPGA IP settings:
Can you tell me what I did wrong?