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WFitt's avatar
WFitt
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3 years ago

eSPI Agent Core, writing response packet to PCTXFIFO

Hi, The Intel eSPI Agent Core is receiving a PC_MEMWR32 (1 byte) packet from the eSPI master, an Intel Elkhart Lake CPU. I am reading out the PCRXFIFO via IP core's Avalon MM bus until RX queue is ...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Not sure if this is related to FPGA question?


Thanks,

Best regards,

Kenny Tan


  • WFitt's avatar
    WFitt
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi,

    My question is relating to Intel eSPI Agent IP core used in Intel FPGA.

    The PCTXFIFO und PCRXFIFO are parts of this IP Core.

    In the IP Core's User's Manual on page 81 there is a short explanation how to use the FIFOs:

    --------------------------------------------------------------------------------
    "You must use the following format while sending the response packet to PCTXFIFO:

    cycletype (SUCCESSFUL_COMPLETION_WITH_DATA/UNSUCCESSFUL_COMPLETION)
    -> MSB length -> LSB length -> DATA (optional)
    After writing a response packet to PCTXFIFO, you must write 1 to Avalon Control
    Register (0x4h), indicating that the PCTXFIFO has a complete payload available.
    Once this flag is triggered, the eSPI host is acknowledged (thru espi status
    information) and fetchs the packet accordingly using the GET_PC command. Each
    FIFO can only store one packet."
    ---------------------------------------------------------------------------------

    I am not shure if I am understanding right and I am sending the right data to the PCTXFIFO (see my initially question).

    Regards

    Wolfram