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WFitt's avatar
WFitt
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3 years ago

eSPI Agent Core, writing response packet to PCTXFIFO

Hi,

The Intel eSPI Agent Core is receiving a PC_MEMWR32 (1 byte) packet from the eSPI master, an Intel Elkhart Lake CPU. I am reading out the PCRXFIFO via IP core's Avalon MM bus until RX queue is empty. I am getting the address and like to respond the associated data. So I am writing the following data in the PCTXFIFO (Ch) :

- Byte 1: 0Fh (cycle type)
- Byte 2: 00h (length MSB)
- Byte 3: 01h (length LSB)
- Byte 4: 55h (Data)

After that I am writing 01h (PCTXFIFO_AVAIL) to the IP core's Control Register (4h).

But the Agent is only sending DEFER, it doesn't send the response with the data.

What am I doing wrong in the processing above?

Regards

Wolfram

13 Replies

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Hi,


    Not sure if this is related to FPGA question?


    Thanks,

    Best regards,

    Kenny Tan


    • WFitt's avatar
      WFitt
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi,

      My question is relating to Intel eSPI Agent IP core used in Intel FPGA.

      The PCTXFIFO und PCRXFIFO are parts of this IP Core.

      In the IP Core's User's Manual on page 81 there is a short explanation how to use the FIFOs:

      --------------------------------------------------------------------------------
      "You must use the following format while sending the response packet to PCTXFIFO:

      cycletype (SUCCESSFUL_COMPLETION_WITH_DATA/UNSUCCESSFUL_COMPLETION)
      -> MSB length -> LSB length -> DATA (optional)
      After writing a response packet to PCTXFIFO, you must write 1 to Avalon Control
      Register (0x4h), indicating that the PCTXFIFO has a complete payload available.
      Once this flag is triggered, the eSPI host is acknowledged (thru espi status
      information) and fetchs the packet accordingly using the GET_PC command. Each
      FIFO can only store one packet."
      ---------------------------------------------------------------------------------

      I am not shure if I am understanding right and I am sending the right data to the PCTXFIFO (see my initially question).

      Regards

      Wolfram

  • hareesh's avatar
    hareesh
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,

    may i know which document are you following because i didn't find related to this "You must use the following format while sending the response packet to PCTXFIFO in that page. if you don't mind please share that document link.


    Thank you,


  • hareesh's avatar
    hareesh
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,

    actually i received different cases related to eSPI with same name. all case from you?


    • WFitt's avatar
      WFitt
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi,

      Yes, I posted my questions relating to eSPI to this forum and to the Intel Premium Support.

      Regards

      Wolfram

    • WFitt's avatar
      WFitt
      Icon for New Contributor rankNew Contributor
      3 years ago

      Thank you, In the meantime I have solved this problem.

      This would have been the answer that I needed:

      In the PCTXFIFO must be written (example):

      - Byte 1: 0Fh (cycle type)
      - Byte 2: 00h (length MSB)
      - Byte 3: 01h (length LSB)
      - Byte 4: 55h (Data)

      Exactly this bytes I wrote in the FIFO.

      I would have enjoyed your confirmation that I was right.

      My problem was caused by my VHDL code reading the PCRXFIFO.

      Now it works fine.

      Regards

      Wolfram

  • hareesh's avatar
    hareesh
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    thanks for update. if you feel your problem is solved i will close this case. please conform


    • WFitt's avatar
      WFitt
      Icon for New Contributor rankNew Contributor
      3 years ago

      You can close the case.

      Regards

      Wolfram

  • hareesh's avatar
    hareesh
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


  • Theja's avatar
    Theja
    Icon for New Contributor rankNew Contributor
    2 years ago


    Hi,
    The Intel eSPI Agent Core is receiving a PUT_MEMRD32_SHORT (1 byte) packet from the eSPI master. I am reading out the Non-posted RX FIFO('h10) via IP core's Avalon MM bus until RX queue is empty. I am getting the address and like to respond the associated data. So I am writing the following data in the NPTXFIFO (14h) :

    - Byte 1: 0Fh (cycle type)
    - Byte 2: 00h (length MSB)
    - Byte 3: 00h (length LSB)
    - Byte 4: 55h (Data)

    After that I am writing 02h (NPTXFIFO_AVAIL) to the IP core's Control Register (4h).

    But the Agent is only sending DEFER, it doesn't send the response with the data.

    Is I am doing in correct way?

    Regards

    Theja

    • WFitt's avatar
      WFitt
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi Theja,

      Yes, you've done it in the right way.

      After the DEFER from the agent the master has to send a GET_PC. Then the agent is responding with ACCEPT and the desired data.

      Unfortunaly, this procedure is unnecessaryly cumbersome. The agent could send the data immediately and not only after a GET_PC.

      So the reading of one byte requires a total of 54 command bytes!!

      - MEMRD32 Command: 8 Byte
      - WAIT_STATE: 16 Byte (default value of the agent IP core)
      - DEFER Reply: 4 Byte
      - GET_PC Command: 2 Byte
      - WAIT_STATE: 16 Byte
      - ACCEPT Reply: 8 Byte