Error: WYSIWYG RAM primitive "ram_block1a0" must have Port A, Data In port or paramet

I think I found it.

I changed the name of an input pin port which feeds the data port of an lpm_fifo, but I forgot to change the name on the fifo's wire.

I should have the error "input port of# ## has no driver" instead of the error with the WYSIWYG RAM but I haven't.

What I have done to find the error is to force the fifo to be made only with Logic Element. With this parameter, I have the good error "input port of# ## has no driver". When this is corrected, I can compile my project with fifo made with either LE or M9K.

strange behavior of quartus....

for info : the fifo is in a sub "bdf file".