Hi,
As I understand it, you observe some issue with Fitter placement. By merely looking at the error messages, it seems like your design has some placement violation. It may be due to limited resource or placement rule violation. To facilitate further debugging, would you mind to further elaborate on the following:
- What is the specific device and Quartus version that you are using?
- What is the specific IPs that you are using ie Native PHY, PCIe HIP and etc?
- Mind share with me high level diagram of your placement within a XCVR bank ie XCVR channel, TX PLL?
Please let me know if there is any concern. Thank you.
New Contributor
