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Altera_Forum
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8 years ago

Error compiling Altera Uart 16550 IP Core Cyclone V

Hello, + Quartus 17 Prime Lite edition + Windows 7 64 bits + Altera 16550 Compatible UART I'm trying to use this module via avalon/axi bus. I added the module via qsys with no problems...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

It seems like FIFO is working OK but not reporting correctly de FIFO size.

I'll debug it a little more using the time-limited SOF.

Thanks for the help!