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FHint
Occasional Contributor
Occasional Contributor"Error 16301 IOPP reference clock is not connected to a clock pin" when trying to use a PLL clock output for EMIF on Arria 10 device
Hello, in a new design I'd like to use Arria 10 External Memory Interface for a DDR3 RAM. The FPGA already has a few input clocks (100 MHz for PCIe refclk, 322 MHz for 10GETH, 40 MHz for core clock...
HI,
EMIF DDR3 IP ref_clk pin must comes from FPGA dedicated PLL_clock_in pin for optimum performance and not from another FPGA internal pll clock output source.
You can read more about PLL ref clock network architecture in A10 EMIF user guide chapter 3.1.8 (page 23)
Thanks.
Regards,
dlim
Deshi_Intel
Regular Contributor
Regular ContributorHI,
EMIF DDR3 IP ref_clk pin must comes from FPGA dedicated PLL_clock_in pin for optimum performance and not from another FPGA internal pll clock output source.
You can read more about PLL ref clock network architecture in A10 EMIF user guide chapter 3.1.8 (page 23)
Thanks.
Regards,
dlim
