BVolaNew Contributor6 years agoError 12006 when compiling clock buffer I have a design instantiating two clock buffers (ALTIOBUF). The design synthesizes fine in Synplify Pro, but when I compile the netlist in Quartus Prime Lite, I get the error: Error (12006): Node ins...Show More
Recent DiscussionsCascaded Avalon Stream Multiplexer in Platform Design does not forward valid data packetsCyclone V CAN triple samplingSolvedR_Tile PCIEAgilex 7 I F-Tile Direct PHY: example TB doesn't workSolvedWhy the Error Response Slave IP cannot work for Agilex 5 SOC FPGA?