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Honored Contributor
Honored ContributorEMIF SDRAM Clock Domain Inquiry
Hi, My goal is to interface my FPGA design with an external DDR3 SDRAM memory using the EMIF IP. I am working off of a sample design, which provided all the parameters for the EMIF (memory clo...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- In particular, the parameters "Memory Clock frequency" is set to 1066.66MHz and the "Clock rate of user logic" is set to quarter rate. I believe this signifies that the EMIF provides an "user clock" of frequency 266MHz, which I am meant to use to clock my design. --- Quote End --- Is that mean I have to connect a 266MHz clock from pin assignment? what if my chip don't have 266MHz clock? If I only have pll_ref_clk 150MHz and, what's different between General->Memory Clock frequency->1066.66MHz and Mem_Timing->Speed bin-> -2133 ?
