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Altera_Forum
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8 years ago

EMIF SDRAM Clock Domain Inquiry

Hi, My goal is to interface my FPGA design with an external DDR3 SDRAM memory using the EMIF IP. I am working off of a sample design, which provided all the parameters for the EMIF (memory clo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

Are you concern about data processing?

If so you can use ping pong method to access memory.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)