Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

EMIF SDRAM Clock Domain Inquiry

Hi, My goal is to interface my FPGA design with an external DDR3 SDRAM memory using the EMIF IP. I am working off of a sample design, which provided all the parameters for the EMIF (memory clo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

--- Quote Start ---

Hi,

Based on datasheet parameters select frequency and use PLL also take care of Timing closer.

Yes can use, Subjected to the datasheet, But Certain frequencies of operation give you the best possible latency based on the memory parameters, You can check the specification of DDR3 and select the frequency required for optimal performance.

--- Quote End ---

Thanks for the response. I will consult the datasheet to see if I can use a lower memory CLK frequency.

Other than this approach, is there any other techniques that are commonly used?