EMIF core clock sharing problem

The confusion here is between the external reference clock and the core clock used for the multiple interfaces. First of all, I'm assuming the two interfaces are in the same I/O column and placed adjacent to each other. Indeed, the external reference clock, must be connected to both interfaces in your RTL. If the interfaces are not adjacent to each other or if intermediate banks are used for extra EMIF lanes or address/control logic, the reference clock will automatically be connected to these intermediate banks.

It sounds like you've set up the core clock master/slave connections correctly, so the issue may be that the two interfaces are not in the same column or that you've put something that uses a different clock in an intermediate I/O bank.