EMIF core clock sharing problem

The documentation is confusing. This paragraph at the bottom of page 161 says that core clock sharing "necessitates" PLL reference clock sharing:

"Core clock sharing necessitates PLL reference clock sharing; therefore, only the

master interface exposes an input port for the PLL reference clock. All slave interfaces

use the same PLL reference clock signal."

And this section near the top of page 161 that describes PLL reference clock sharing says this:

"To implement PLL reference clock sharing, open your RTL and connect the PLL

reference clock signal at your design's top-level to the PLL reference clock port of

multiple interfaces."

So if core clock sharing "necessitates" PLL reference clock sharing then why do the slaves not expose the reference clock port? From the error message it seems pretty clear that the slaves do need a reference clock. I recommend opening a service request with Intel to get some clarification. Or maybe you'll get lucky and get a response here.