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User1580871742356367's avatar
User1580871742356367
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

EMIF controller and DDR4

Like to confirm who's programming the DDR4 MMR registers. The Memory controller engine alone(without SW or SW (e.g. uboot etc.) ? Thanks.
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Sir,


Thanks Simon for providing the explanations.


The Memory Mode Register (MMR) interface is the Avalon based interface through which core can access debug signals and sideband operation requests in the hard memory controller.


Do you have further question about this?


Regards,

Adzim


  • User1580871742356367's avatar
    User1580871742356367
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Yes, I have one more question, where was the arf_to_valid parameter or value got from by Quatus Pro.

    I mean which timing settings in the EMIF generator.

    I didn't see it in the emif.xml nor hps.xml.