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gcohe5's avatar
gcohe5
Icon for New Contributor rankNew Contributor
6 years ago

emif burst size configuration

hi I'm using a Arria 10 development kit with a DDR4 memory. I want to enable a burst size of 1024 (the maximum the avalon bridge ip allows). The EMIF connected to the HPS is configured to burst s...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello Sir,

I think there are misunderstanding. The BL that you are seeing in this GUI is the BL between FPGA and the SDRAM device.

I believe you are interest on the Burst length on the local interface (Avalone -MM).

If yes, it is actually support 128Bits. See this document:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf#page=36

You do not need to set the local burst length value when you generate the IP. The IP will generate the local interface with the burstcount signals with 7 bits which is equal to 128.