Forum Discussion
New ContributorEMIF Avalon-MM Burst never ending
Hi,
I think the busrtbegintransfer signal no longer used in Arria 10 device.
The signal exist to support legacy memory controllers.
Most of the avalon interfaces got some details in the Avalon Interface Specifications: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/memory-mapped-interface-signal-roles.html
About the clocks, the PLL_REF_CLK should be the clock source for EMIF IP.
The EMIF IP can provide the clock to user logic through the EMIF_USR_CLK.
You may feed your logic with this clock.
The chip select for EMIF interface is between FPGA and external memory.
https://www.intel.com/content/www/us/en/docs/programmable/683106/21-1-19-2-0/mem-for-ddr4.html
Regards,
Adzim
New ContributorHi,
It works !
I removed the chipselect signal from my master and there is no parasitic "read" anymore.
It is very good to know that even though there is no chipselect input on a slave, it can affect its behavior. I'm curious to know how avalon automatically assigns a signal which is not supported by slave ! Anyway, that is a very good practice to be consistant between master/slaves.
Thank you very much,
Regards,
RLeduc
