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BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
9 months ago
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EMIF - ref_clk from a bank other than address control and share that ref clock for 2 EMIF instances

Hi, I am using a Stratix 10 1SG10MHN3F74C2LG dual die FPGA on our board. Each die has two EMIF instances. Each EMIF instance uses reference clock fed from the clk pins in the address control IO Ban...
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  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    8 months ago

    Hi Bharat,


    Unfortunately, the ref_clk need to be placed within the Address and Command group.

    Sharing the pin to other EMIF IP is permitted but need to follow the rules.


    Regards,

    Adzim


AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
9 months ago

Hi Bharat,


The User Guide has some guidelines when sharing the PLL Reference Clock between multiple EMIF interfaces.

Here is the link to User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683741/24-1-19-2-8/resource-sharing-guidelines-multiple-01.html


Based on the User Guide, you should place the ref_clk in Address/Command group, in the same column and the EMIF IP should has similar frequency.

You need to choose a different pin location for ref_clk that located within the Address/Command group.

You also need to connect the same signal in RTL code.


Regards,

Adzim