Contributor
Regular ContributorHi HPB,
Regarding your latest inquiries on the txuserclock, please correct me if I am wrong, I believe you are referring to the XCVR-core parallel clock ie tx_clkout. If yes, as I understand it, when the TX is put to elecical idle, the tx_clkout should be still valid as it is derived from the TX PLL which is still working.
Regarding the loopback, since there is no valid data received by RX, the CDR would not be able to lock-to-data. It will remain locking to its own reference clock and the rx_clkout will be derived from its own reference clock.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
ContributorHi Chee Pin,
Yes, I was talking about parallel clock.
I am convinced that tx_clkout will be valid as it is generated by local ATX PLL.
On the receiver side, I am not clear about "remain locking to its own reference clock" .
Does this mean that Lock-to-Reference Mode (rx_is_lockedtoref =1)? If this is true, then frequency of rx_clkout is same as frequency of reference clock?
With an example, I will explain my understanding. Please correct me if I am wrong.
Reference clock frequency = 156.25Mhz
Before RX receives electrical IDLE, it was locked to data @ 20Gbps data rate & 64-bit interface. So rx_clkout = 20G/64 = 312.5MHz.
When RX receives electrical IDLE, then there is no data toggling and hence rx losses lock to data. Then rx_clkout will be only locked to its reference clock. Whether that means, rx_clkout will be changed to 156.25MHz from 312.5MHz?
If the corresponding TX is out of electrical IDLE, then RX again locks to data and switches back to 312.5Mhz?
With Regards,
HPB
