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HBhat2
Contributor
ContributorElectrical IDLE in Transceiver
Hi, My requirement is keep the transceiver lines in Electrical Idle whenever the Logical Layer FSM goes into low power state. I found that we can select "Enable tx_PMA_elecidle port" under TX PMA ...
HBhat2Contributor
ContributorHi,
I need one clarification regarding below point.
a) What is the behavior of Transceiver p/n lines when I drive tx_PMA_elecidle = 1;
[CP] The transmitter will be tri-stated when this signal is driven high.
When transmitter is tri-stated, whether common mode voltage will be maintained in the transmitter line (note that I am not enabling any PIPE/PCIe related settings, instead Native PHY will be configured with PCS Direct mode)?
With regards,
HPB
HBhat2Contributor
ContributorHi,
Also, when Transmitter in Electrical IDLE, whether txuserclock toggling will be valid?
If the Transmitter in electrical IDLE is loopback to a receiver, In this case, receiver also provide valid rxuserclock as required to configured data rate?
With regards,
HPB
