Contributor
Regular ContributorHi HPB,
Thanks for your update. As I understand it, you are using Enhanced PCS and thus the rx signal detect feature is not available. In this case, you may use the CDR lock-to-data status to tell if the TX has gone into electrical idle state. Additional info to share is that the CDR lock-to-data status will toggle when there is no valid data. Only when the assertion remain high for more than 4us would indicate the CDR has achieve LTD.
Regarding the RX data valid signal from the FIFO, this is part of the FIFO which is after the CDR. Thus, I think using CDR lock status would be more appropriate.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
ContributorHi,
"
I understand that whenever transmitter is active both lock to data & lock to ref are asserted (1). Whenever the transmitter goes into electrical IDLE, the lock to data status in the corresponding receiver in the other side goes low (de-asserted) and receiver will continue to lock to ref only. Whenever the linked transmitter exits electrical IDLE, the CDR status of the receiver (lock to data) asserted again.
"
That means above understanding is correct & based on lock to data de-assertion & assertion, I can arrive at the conclusion that corresponding TX is in IDLE or not. [Apart from some delay to assert & de-assert the status]
With regards,
HPB
Regular ContributorContributorHi,
Thanks for clarification. The toggling may not have any particular duration right? Is it possible to know what is the maximum time the LTD will be high (during toggling LTD will become High for some time & low for some time) although no valid data is present at RX?
With Regards,
HPB
Regular ContributorContributorHi @cheepinc_Intel ,
Thanks for pointing towards the reset chapter.
Yes, I observed tLTD time (min 4us). As per the reset chapter, if LTD is high for min tLTD time, then it is assured that rx is getting valid data.
Also, 5.1.6.2. Lock-to-Data Mode of Arria 10 transceiver user guide,
The rx_is_lockedtodata signal toggles until the CDR sees valid data; therefore, you should hold receiver PCS logic in reset (rx_digitalreset) for a minimum of 4 μs after rx_is_lockedtodata remains continuously asserted.
With this I can conclude that,
Whenever the link is active, & suddenly if LTD is de-asserted, that means the TX is in electrical IDLE (by considering there is no disturbance to physical channel/connectivity). This is the indication that RX is not receiving valid data. And after some time, if TX comes out of electrical IDLE and starts sending the data, RX side look for the assertion of LTD and monitor that for atleast 4us the LTD gets asserted. If yes, then corresponding TX is out of Electrical-IDLE .
With Regards,
HPB
Regular Contributor
