Forum Discussion
Hi HPB,
As I understand it, you have some inquiries related to using RX CDR LTD status to detect when the TX is being put into electrical idle. For your information, the CDR might take some time before it lose lock to data and de-assert the LTD. I would like to recommend you to explore into using the rx_std_signaldetect signal to detect the TX electrical idle. Whenever the TX is in elecidle, there should be no valid signal arrive at the RX. The RX signal detect will de-assert. Note that you would need to configure the signal detect threshold to the right settings to ensure normal operation of your link.
For your reference, as per the A10 user guide, in SATA application, the following values are used:
For SR: sd_threshold for SATA = SDLV_4
For LR: sd_threshold for SATA = SDLV_6
Also, you would need to have 8b10b block enabled when you are using this signal detect.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
- HBhat25 years ago
Contributor
Hi @cheepinc_Intel ,
Thanks for the response & options.
rx_std_signaldetect : This port is accessible when I select PCIe configuration. In my development, I am using Basic (Enhanced PCS) mode as I am writing my own custom PCS for the protocol. So, I think rx_std_signaldetect may not be useful for me.
One more thing, whether is it possible to use rx_data_valid port for the same purpose (to know whether the connected TX is in electrical IDLE or not) ?
With Regards,
HPB