editing hbm2 example design and simulating the new design.

Hi Sir,

Thank you for joining this Intel Community.

HBM2 is integrated into Intel FPGA Stratix 10 MX devices using System In Package (SiP) technology. Devices include either 1 or 2 HBM2 stacks at the top and bottom of the package, and each stack is either 4 high or 8 high. Each HBM2 connected to an EMIB interface has a dedicated hard controller that can be customized for each physical channel. The controllers are connected to a Universal Interface Bus, or UIB, to access the EMIB to the memory. You may refer to this HBM2 UG for more details :

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20031.pdf

Feel free to check out this online training for an overview of the HBM architecture and implementation:

https://www.intel.com/content/www/us/en/programmable/support/training/course/ohbms10.html

Upon completing this course, we recommend the following two follow-on courses:

• High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices: HBMC Features
• High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices: Implementation

Regarding the example design, may I know what kind of changes made and which file are you referring to?

Thanks

Regards,

Aida