Forum Discussion
Occasional ContributorE-Tile TX/RX out clock constraint
Michael,
Apologize for the late reply on this. You can try to refer to the following UG to find some of the E-Tile hard IP example designs which were validated by engineering.
See if it is helpful.
Super ContributorAlso, can you double check the user guide and reference design for the constrain needed?
Occasional ContributorHi Kenny,
I'm using the Stratix 10 SM16BEU2 device.
"What you need to do is create clock at the port and use derive_pll_clocks to generate the correct output clocks."
Which port should have this create_clock constraint?
I already tried a lot ports in the E-Tile native to constraint but without success.
Best regards,
Michael
- MichaelB
Hi,
is there anyone who could help me with this topic?
I'm still not able to assign any create_clock constraint on the E-Tile TX/RX output clock to support different frequencies and data rates.
Best regards,
Michael
