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MichaelB's avatar
MichaelB
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

E-Tile TX/RX out clock constraint

Hi, I've defined a data rate in my E-Tile IP and I want to switch the data rate using the E-Tile Avalon reconfiguration interface by setting the internal PLL multiplier. Now I have chosen the ...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

Also, can you double check the user guide and reference design for the constrain needed?


  • MichaelB's avatar
    MichaelB
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi Kenny,

    I'm using the Stratix 10 SM16BEU2 device.

    "What you need to do is create clock at the port and use derive_pll_clocks to generate the correct output clocks."

    Which port should have this create_clock constraint?

    I already tried a lot ports in the E-Tile native to constraint but without success.

    Best regards,

    Michael

    • MichaelB's avatar
      MichaelB
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi,

      is there anyone who could help me with this topic?

      I'm still not able to assign any create_clock constraint on the E-Tile TX/RX output clock to support different frequencies and data rates.

      Best regards,

      Michael