Forum Discussion
Occasional ContributorE-Tile frequency constraints
Hi,
If you observe issue trying to constrain the output clock ie cannot find in tech map, would you mind to help opening a new Forum case and let me know the case. I will help to route to our timing team to better assistance. Thank you.
Regular ContributorHi,
Based on my understanding, normally we would constraint the input XCVR refclk and the TimeQuest should be able to auto-populate the PLL derived clocks. For previous device family, we need to add a derive_pll_locks SDC but I think for S10 device, it is no longer needed. Can you try constraining the refclk and check if the parallel output are auto-populated?
Thank you.
- MichaelB
Hi,
I'm planning to use the same reference clock for all configurations. To achieve the different data rates I'm just programming the PLL multiplier value using the Avalon reconfiguration interface.
Do I have to set the constraint to the PLL output of the XCVR?
Best regards,
Michael
