Forum Discussion
Occasional ContributorE-Tile frequency constraints
Hi,
If you observe issue trying to constrain the output clock ie cannot find in tech map, would you mind to help opening a new Forum case and let me know the case. I will help to route to our timing team to better assistance. Thank you.
Super ContributorCan you put down the sdc file that you have written?
Also, did you get timing violation?
I think the frequency that you are trying to archive is too fast. So, the constrain might not be applicable anymore as those constrain are for core but not periphery.
Occasional ContributorHi Kenny,
thx for your response!
Constraints file:
create_clock -period 7.716049382716049 -name clk_high_freq [get_ports {u0|etile|*x_clkout|ch*}]
create_clock -period 20.83333333 -name clk_low_freq [get_ports {u0|etile|*x_clkout|ch*}] -add
At first those ports are not recognised for create_clock but for clock_groups it does which I don't get.
Furthermore the period will be truncated which makes me a little bit worried to hit the required frequency.
I'd really like to set the lower frequency as default (in IP file for data rate) and constraint the clocks to its maximum frequency.
Timing violations are not present right now because I used the lower frequency as default a create_clock constraint won't be recognised and is invalid because the port does not exists.
For create_clock_group it does work.
Do you have any hints how to solve the truncation and the create_clock to the given ports?
Best regards,
Michael
