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MichaelB's avatar
MichaelB
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

E-Tile frequency constraints

Hi, I've a question regarding the E-Tile transceiver and their constraints. I would like to implement different data rates which I have already tested successfully using the reconfiguration int...
  • CheepinC_altera's avatar
    CheepinC_altera
    5 years ago

    Hi,


    If you observe issue trying to constrain the output clock ie cannot find in tech map, would you mind to help opening a new Forum case and let me know the case. I will help to route to our timing team to better assistance. Thank you.


CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Please correct me if I am wrong, as I understand it, your specific inquiry is related to the tx/rx output clock constraint for different data rate. If yes, please allow me some time to consult our timing expert on this to if there is any guide or documentation on multi data rate constraint. For your information, I am more towards transceiver PHY and hardware instead of timing.


Just would like to check with which specific parallel output clock of Native PHY that you are trying constrain?


Please let me know if there is any concern. Thank you.


MichaelB's avatar
MichaelB
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi CheePin,

thanks for your response!

Yes I'm referring to the parallel data clock (tx/rx out clk) of the Native PHY.

Best regards,

Michael