Dual Port RAM

"I see q changes -98 1 cycle after read address 3m w/o output registered."

When clock trigger, store_sin is 0 due to delay of fsin_o. So, the DRAM, save the 0 instead of -98 at address 3.

However, i still have some question on the wo output registered. It is because i find out that q is immediate changing(few ns delay) instead of clock triggering for a simple design.

Any idea on this?

"Read address 3 is 2 cycles after write address 3, was it supposed to be 1 cycle later instead of 2?"

You are right if you want read the data immediately and it actually depends on the application that when to read the data.