DSPBuilder signaltap tuning

Hi Yan:

During synthesis, sometimes if the clock is not driving other logic in you design, synthesis will remove and/or rename the signal, and then signaltap won't find it.

My guess is this is what's happening, When you build a simple clock divider outside of the PLL, it is made up a of register, that feeds back to itself, so it won't get optimized out. and since it's a register, it's easier to find.

Inherently there's nothing wrong with using a PLL generated divider.

Pete