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Honored Contributor
Honored ContributorDSPBuilder signaltap tuning
Hi, I try to check correction of data from audio codec with signaltap on 2S60 DK. How can I decrease rate of data assigns to signaltap memory in dspbuilder model. I put signaltap block before ...
Altera_ForumHonored Contributor
Honored ContributorHi Pete, Thank you very much again. It works properly.:) I made clock division by PLL and signaltap clock doesn't recognize PLL's clock. why? What the difference between clock divider and PLL principally?:confused: Clock divider takes clock form CLOCK DRIVER chip? King regards, Yan
