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Altera_Forum
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13 years agoI actually did that , but there is no signal at the FPGA pin, I also did it with a PLL which generates internal clocks with frequencies that are multiples of the frequency of the system clock
And set pin out with the Quartus II Pinout Assignments: Pin name : PLL_clk0 Pin location : Pin_F3 And I get this Matlab Error Pin Assignment Error: Port PLL_clk0 referenced in Pin Assignment dspddcejem/Quartus II Pinout Assignments cannot be found. Error: Error during compilation: Error: Error analyzing model see log for details. What am I doing wrong? Do I have to include a output port?