Forum Discussion
Altera_Forum
Honored Contributor
17 years agoHi - thank you for the quick answer
My problem is that I would like to load a vector generated in Matlab and then access it via the FPGA. I have managed to load the vector into simulink and store it in RAM, but I would really like to have a more "free" access to each element of the vector. My problem is that I have 4 different variabels which I use to index the vector with. I have thought of a solution where I have a mux block which will choose which of the four variables index the RAM. Depending on which index variabel I use the output will have to be loaded to different adders. Therefore I will need a demux block after the RAM. Unfortunately this solution will require a lot of control. Therefore I would like to know if it possible to get a register which I can access independently of the other registers? -thanks