Doing a 32-bit access through an Avalon 32-bit Bridge to a 16-bit wide Avalon MM SDRAM Controller slave doesn't seem to follow the Avalon Dynamic Bus Sizing in my QSYS design.

There are no screenshot attached, can you reattached it?

Did your ​SDRAM Controller design with a byte enable?

Avalon-MM moves data in the form of symbols using addresses to determine destination

-Symbols are typically bytes (i.e. 8 bits)

-Masters cannot access slaves of a different symbol size

-Without master byte enables Qsys assumes master is always accessing full words